1. Technical Field
Example embodiments of the present invention relate to a method of manufacturing a semiconductor device. More particularly, example embodiments of the present invention relate to a semiconductor device having multiple channels and a method of manufacturing a semiconductor device including a MOS transistor that has multiple channels.
2. Description of the Related Art
As semiconductor devices have been highly integrated, a size of a region where devices are formed, i.e., an active region may be reduced. Further, a channel length of a metal-oxide-semiconductor (MOS) transistor in the active region may be shortened. When the channel length of the MOS transistor is short, source/drain regions may greatly affect an electric field and/or an electric potential in the channel region. This phenomenon may be referred to as a short channel effect.
Therefore, various methods of reducing sizes of devices on a semiconductor substrate, and also methods of improving capacities thereof have been widely researched. A conventional example of the methods may include a vertical transistor such as a fin structure, a fully depleted lean-channel transistor (DELTA) structure, a gate-all-around (GAA) structure, etc.
For example, U.S. Pat. No. 6,413,802 discloses a fin-type MOS transistor that includes a plurality of thin channel fins that are in parallel with each other and arranged between source/drain regions, and a gate electrode expanding along an upper face and sidewalls of the channel fins. According to the fin-type MOS transistor, since the gate electrode is formed on both sidewalls of the channel fins, the gate electrode may be controlled from the sidewalls so that the short channel effect may be decreased. However, because the channel fins of the fin-type MOS transistor are arranged in parallel with a widthwise direction of the gate electrode, areas of channel regions and the source/drain regions may become greater. Further, a junction capacitance of the source/drain regions may be increased due to a number of the channels.
U.S. Pat. No. 4,996,574 discloses a MOS transistor having the DELTA structure. In the MOS transistor having the DELTA structure, an active layer as a channel may have a uniform width and a vertically protruded channel region. Further, a gate electrode may surround the vertically protruded channel region. Thus, a height of the protruded channel region may correspond to a width of the channel, and a width of the protruded channel region may correspond to a thickness of the channel. Since both sidewalls of the protruded channel region may be used together, the channel width may increase twice as much. Furthermore, when the width of the protruded channel region is reduced, depletion layers of the channel at both sidewalls may be overlapped with each other to increase an electrical conductivity of the channel.
However, when the MOS transistor having the DELTA structure is formed on a bulk silicon substrate, a substrate may be oxidized when forming a protruded portion at a surface of the substrate where the channel is to be formed, and covering the protruded portion with an anti-oxidation layer. Here, when the oxidation process is carried out, a portion between the protruded portion and the substrate, which is not covered with the anti-oxidation layer, may be oxidized by laterally diffusing oxygen so that the channel may be isolated from the substrate. The excessive oxidation may cause the channel isolation and reduce a thickness of the channel adjacent to the portion between the protruded portion and the substrate. Further, a single crystalline layer in the portion between the protruded portion and the substrate may be damaged by stresses generated in the oxidation process.
In contrast, when the MOS transistor having the DELTA structure is formed on a silicon-on-insulator (SOI) substrate, an SOI layer may be etched to provide the etched SOI layer with a narrow width, thereby forming a channel region. Thus, the above-mentioned problems caused by the excessive oxidation of the bulk substrate may not be generated. However, a width of the channel may be restricted by a thickness of the SOI layer in the SOI substrate. Since the SOI layer in a full depletion type SOI substrate may have hundreds of angstroms of thickness, applications of the SOI substrate may be very limited.
In the MOS transistor having the GAA structure, an active channel pattern as an SOI layer may be formed on a substrate. A gate electrode may surround a channel region of the active channel pattern covered with a gate insulation layer. Thus, effects substantially similar to those of the DELTA structure may be obtained.
However, to embody the GAA structure, a buried oxide layer under the active channel pattern may be etched using an undercut of an isotropic etching process to surround the active channel pattern in the channel region with the gate electrode. Here, since the SOI layer may be used for the channel region and source/drain regions, most lower portions of the source/drain regions as well as a lower portion of the channel region may be removed by the isotropic etching process. Therefore, when a conductive layer for the gate electrode is formed, the gate electrode may be formed at the lower portions of the source/drain regions as well as the channel region so that a parasitic capacitance may be increased.
Further, the lower portion of the channel region may be horizontally etched during the isotropic etching process. As a result, a horizontal length or a width of a tunnel with which the gate electrode is filled during a subsequent process may be lengthened. Thus, it may be difficult to manufacture the MOS transistor having the gate length shorter than the channel width. Further, there may be limitations to shortening the gate length.
A multi-bridge-channel MOS transistor has been developed as an alternative plan for overcoming the above-mentioned limits. The multi-bridge-channel MOS transistor may be manufactured by forming an active channel pattern that includes tunnels penetrating between channels, surrounding the channels with a gate electrode to thereby fill up the channels, and forming source/drain regions connected to the channels. Thus, although the number of the channels is various, the source/drain regions may have a uniform junction capacitance so that the multi-bridge-channel MOS transistor may have an improved integration degree and high speed.
However, in the multi-bridge-channel MOS transistor, a mask pattern structure, which may be used as a mold pattern for forming the gate electrode, may not be removed after forming the gate electrode. The remaining mask pattern structure may be used as a portion of an insulation interlayer. Therefore, it may be difficult to perform a silicidation process for reducing resistances of the source/drain regions on the source/drain regions. Further, since a process for forming the source/drain regions by implanting ions into the source/drain regions may be carried out before forming the mask pattern structure, the ions in the source/drain regions may have a heat budget that may induce a thermal diffusion of the ions by heat during formation of the gate electrode. As a result, the thermal diffusion of the ions may result in a short channel length between the source/drain regions so that an electrical short between the source/drain regions under a lowermost layer of the gate may be generated.